Language Breakdown
Lines of code distribution across 17 owned repositories
T-Shaped Developer
T-shapedDeep in Verilog with broad versatility
Collaboration Network
Global Impact visualization
Repos
28
PRs
0
Growth
+18%
Top Collaborators
No collaborator data yet.
Coding Streak
Contribution activity over the past year
Adam Majmudar
@adam-maj
Adam Taylor
@ATaylorCEngFIET
George Yu
@georgeyhere
Goran Mahovlic
@goran-mahovlic
Top Repositories
Opensource DDR3 Controller
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
My notes for DDR3 SDRAM controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
Open Source Impact
Contributions to external projects
